(a) Field
The invention relates to a thin film transistor array panel and a liquid crystal display including the same. More particularly, the invention relates to a thin film transistor array panel in which overlapping areas between gate electrodes and source/drain electrodes are constant even when masks are erroneously aligned during a forming process thereof, and a liquid crystal display including the same.
(b) Description of the Related Art
A liquid crystal display (“LCD”) is one of flat panel displays that are widely used. The LCD device is comprised of two substrates with electrodes therein, and a liquid crystal layer interposed therebetween to control the transmittance of light that passes through the liquid crystal layer by applying signals to the electrodes to rearrange liquid crystal molecules of the liquid crystal layer.
The LCD includes a thin film transistor array panel and a common electrode panel which oppose each other. The thin film transistor array panel includes gate lines that transmit a gate signal and data lines that transmit a data signal intersecting with each other, thin film transistors connected to the gate lines and the data lines, and pixel electrodes connected to the thin film transistors. The common electrode panel includes a light blocking member, a color filter, and a common electrode.
However, the LCD has some disadvantages in visibility and a viewing angle, and thus various modes of LCDs have been developed in order to address these disadvantages. While some improvement in the visibility and the viewing angle has been achieved, there are still further challenges in that a desired pattern of elements within the LCD is not properly formed due to misalignment of a mask during a forming process thereof.
In forming the LCD, an overlapping area between the gate electrode and source/drain electrode may be varied due to the misalignment of the mask. Further, when the thin film transistors are formed in a zigzag arrangement with respect to the data lines, the overlapping area between the gate electrode and the source/drain electrode is increased in one region, but the overlapping area between the gate electrode and the source/drain electrode is decreased in another region. Accordingly, a striped pattern may disadvantageously occur in a vertical (e.g., perpendicular) direction to the data line.